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Pcornat 2025-02-10 21:31:02 +01:00
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Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h Normal file
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Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h Normal file
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/**
******************************************************************************
* @file stm32l4xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_H
#define STM32L4xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_conf.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Types HAL Exported Types
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
#define SYSCFG_BOOT_MAINFLASH 0U
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4P5xx || STM32L4Q5xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2)
#define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0)
#else
#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/**
* @}
*/
/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
* @{
*/
#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
/**
* @}
*/
/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
* @{
*/
#define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
#define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
#define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
#define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
#define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
#define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
#define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
#define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
#define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
#define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
#define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
#define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
#define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
#define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
#define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
#define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
#if defined(SYSCFG_SWPR_PAGE31)
#define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
#define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
#define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
#define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
#define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
#define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
#define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
#define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
#define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
#define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
#define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
#define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
#define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
#define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
#define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
#define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
#endif /* SYSCFG_SWPR_PAGE31 */
/**
* @}
*/
#if defined(SYSCFG_SWPR2_PAGE63)
/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)
* @{
*/
#define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
#define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
#define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
#define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
#define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
#define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
#define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
#define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
#define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
#define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
#define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
#define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
#define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
#define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
#define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
#define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
#define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
#define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
#define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
#define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
#define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
#define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
#define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
#define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
#define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
#define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
#define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
#define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
#define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
#define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
#define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
#define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
/**
* @}
*/
#endif /* SYSCFG_SWPR2_PAGE63 */
#if defined(VREFBUF)
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */
/**
* @}
*/
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SYSCFG_flags_definition Flags
* @{
*/
#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */
#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */
/**
* @}
*/
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#endif
#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP)
#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP)
#endif
#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#endif
#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#endif
#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#endif
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
*/
/** @brief Main Flash memory mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief System Flash memory mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
/** @brief Embedded SRAM mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
/* STM32L496xx || STM32L4A6xx || */
/* STM32L4P5xx || STM32L4Q5xx || */
/* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
/** @brief OCTOSPI mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2))
#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0))
#else
/** @brief QUADSPI mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/**
* @brief Return the boot mode as configured by user.
* @retval The boot mode as configured by user. The returned value can be one
* of the following values:
* @arg @ref SYSCFG_BOOT_MAINFLASH
* @arg @ref SYSCFG_BOOT_SYSTEMFLASH
@if STM32L486xx
* @arg @ref SYSCFG_BOOT_FMC
@endif
* @arg @ref SYSCFG_BOOT_SRAM
@if STM32L422xx
* @arg @ref SYSCFG_BOOT_QUADSPI
@endif
@if STM32L443xx
* @arg @ref SYSCFG_BOOT_QUADSPI
@endif
@if STM32L462xx
* @arg @ref SYSCFG_BOOT_QUADSPI
@endif
@if STM32L486xx
* @arg @ref SYSCFG_BOOT_QUADSPI
@endif
*/
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief SRAM2 page 0 to 31 write protection enable macro
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
* @note Write protection can only be disabled by a system reset
*/
#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
}while(0)
#if defined(SYSCFG_SWPR2_PAGE63)
/** @brief SRAM2 page 32 to 63 write protection enable macro
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
* @note Write protection can only be disabled by a system reset
*/
#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\
}while(0)
#endif /* SYSCFG_SWPR2_PAGE63 */
/** @brief SRAM2 page write protection unlock prior to erase
* @note Writing a wrong key reactivates the write protection
*/
#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\
SYSCFG->SKR = 0x53;\
}while(0)
/** @brief SRAM2 erase
* @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
*/
#define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
/** @brief Floating Point Unit interrupt enable/disable macros
* @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts
*/
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
}while(0)
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
}while(0)
/** @brief SYSCFG Break ECC lock.
* Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
* Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
/** @brief SYSCFG Break PVD lock.
* Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
/** @brief SYSCFG Break SRAM2 parity lock.
* Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked by system reset.
*/
#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
/** @brief Check SYSCFG flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
* @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
*/
#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of :
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
* @{
*/
#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
((__CONFIG__) == SYSCFG_BREAK_PVD) || \
((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL))
#if defined(VREFBUF)
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#endif /* VREFBUF */
#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#elif defined(SYSCFG_FASTMODEPLUS_PB8)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
#elif defined(SYSCFG_FASTMODEPLUS_PB9)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#else
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
#endif
/**
* @}
*/
/**
* @}
*/
/* Exported variables --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group3
* @{
*/
/* DBGMCU Peripheral Control functions *****************************************/
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group4
* @{
*/
/* SYSCFG Control functions ****************************************************/
void HAL_SYSCFG_SRAM2Erase(void);
void HAL_SYSCFG_EnableMemorySwappingBank(void);
void HAL_SYSCFG_DisableMemorySwappingBank(void);
#if defined(VREFBUF)
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
#endif /* VREFBUF */
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_H */

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Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h Normal file
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@ -0,0 +1,422 @@
/**
******************************************************************************
* @file stm32l4xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_CORTEX_H
#define STM32L4xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
1 bit for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
0 bit for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and Configuration functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2) || \
((TYPE) == MPU_TEX_LEVEL4))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_CORTEX_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DEF_H
#define STM32L4xx_HAL_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00,
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/
#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#endif /* UNUSED */
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1)
/* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler V5 */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6
--------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_DEF_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_dma.h
* @author MCD Application Team
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DMA_H
#define STM32L4xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
/**
* @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Request; /*!< Specifies the request selected for the specified channel.
This parameter can be a value of @ref DMA_request */
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
} HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
} HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
} HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
#if defined(DMAMUX1)
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
#endif /* DMAMUX1 */
} DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{
*/
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
/**
* @}
*/
/** @defgroup DMA_request DMA request
* @{
*/
#if !defined (DMAMUX1)
#define DMA_REQUEST_0 0U
#define DMA_REQUEST_1 1U
#define DMA_REQUEST_2 2U
#define DMA_REQUEST_3 3U
#define DMA_REQUEST_4 4U
#define DMA_REQUEST_5 5U
#define DMA_REQUEST_6 6U
#define DMA_REQUEST_7 7U
#endif
#if defined(DMAMUX1)
#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
#define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#define DMA_REQUEST_ADC2 6U /*!< DMAMUX1 ADC1 request */
#define DMA_REQUEST_DAC1_CH1 7U /*!< DMAMUX1 DAC1 CH1 request */
#define DMA_REQUEST_DAC1_CH2 8U /*!< DMAMUX1 DAC1 CH2 request */
#define DMA_REQUEST_TIM6_UP 9U /*!< DMAMUX1 TIM6 UP request */
#define DMA_REQUEST_TIM7_UP 10U /*!< DMAMUX1 TIM7 UP request */
#define DMA_REQUEST_SPI1_RX 11U /*!< DMAMUX1 SPI1 RX request */
#define DMA_REQUEST_SPI1_TX 12U /*!< DMAMUX1 SPI1 TX request */
#define DMA_REQUEST_SPI2_RX 13U /*!< DMAMUX1 SPI2 RX request */
#define DMA_REQUEST_SPI2_TX 14U /*!< DMAMUX1 SPI2 TX request */
#define DMA_REQUEST_SPI3_RX 15U /*!< DMAMUX1 SPI3 RX request */
#define DMA_REQUEST_SPI3_TX 16U /*!< DMAMUX1 SPI3 TX request */
#define DMA_REQUEST_I2C1_RX 17U /*!< DMAMUX1 I2C1 RX request */
#define DMA_REQUEST_I2C1_TX 18U /*!< DMAMUX1 I2C1 TX request */
#define DMA_REQUEST_I2C2_RX 19U /*!< DMAMUX1 I2C2 RX request */
#define DMA_REQUEST_I2C2_TX 20U /*!< DMAMUX1 I2C2 TX request */
#define DMA_REQUEST_I2C3_RX 21U /*!< DMAMUX1 I2C3 RX request */
#define DMA_REQUEST_I2C3_TX 22U /*!< DMAMUX1 I2C3 TX request */
#define DMA_REQUEST_I2C4_RX 23U /*!< DMAMUX1 I2C4 RX request */
#define DMA_REQUEST_I2C4_TX 24U /*!< DMAMUX1 I2C4 TX request */
#define DMA_REQUEST_USART1_RX 25U /*!< DMAMUX1 USART1 RX request */
#define DMA_REQUEST_USART1_TX 26U /*!< DMAMUX1 USART1 TX request */
#define DMA_REQUEST_USART2_RX 27U /*!< DMAMUX1 USART2 RX request */
#define DMA_REQUEST_USART2_TX 28U /*!< DMAMUX1 USART2 TX request */
#define DMA_REQUEST_USART3_RX 29U /*!< DMAMUX1 USART3 RX request */
#define DMA_REQUEST_USART3_TX 30U /*!< DMAMUX1 USART3 TX request */
#define DMA_REQUEST_UART4_RX 31U /*!< DMAMUX1 UART4 RX request */
#define DMA_REQUEST_UART4_TX 32U /*!< DMAMUX1 UART4 TX request */
#define DMA_REQUEST_UART5_RX 33U /*!< DMAMUX1 UART5 RX request */
#define DMA_REQUEST_UART5_TX 34U /*!< DMAMUX1 UART5 TX request */
#define DMA_REQUEST_LPUART1_RX 35U /*!< DMAMUX1 LP_UART1_RX request */
#define DMA_REQUEST_LPUART1_TX 36U /*!< DMAMUX1 LP_UART1_RX request */
#define DMA_REQUEST_SAI1_A 37U /*!< DMAMUX1 SAI1 A request */
#define DMA_REQUEST_SAI1_B 38U /*!< DMAMUX1 SAI1 B request */
#define DMA_REQUEST_SAI2_A 39U /*!< DMAMUX1 SAI2 A request */
#define DMA_REQUEST_SAI2_B 40U /*!< DMAMUX1 SAI2 B request */
#define DMA_REQUEST_OCTOSPI1 41U /*!< DMAMUX1 OCTOSPI1 request */
#define DMA_REQUEST_OCTOSPI2 42U /*!< DMAMUX1 OCTOSPI2 request */
#define DMA_REQUEST_TIM1_CH1 43U /*!< DMAMUX1 TIM1 CH1 request */
#define DMA_REQUEST_TIM1_CH2 44U /*!< DMAMUX1 TIM1 CH2 request */
#define DMA_REQUEST_TIM1_CH3 45U /*!< DMAMUX1 TIM1 CH3 request */
#define DMA_REQUEST_TIM1_CH4 46U /*!< DMAMUX1 TIM1 CH4 request */
#define DMA_REQUEST_TIM1_UP 47U /*!< DMAMUX1 TIM1 UP request */
#define DMA_REQUEST_TIM1_TRIG 48U /*!< DMAMUX1 TIM1 TRIG request */
#define DMA_REQUEST_TIM1_COM 49U /*!< DMAMUX1 TIM1 COM request */
#define DMA_REQUEST_TIM8_CH1 50U /*!< DMAMUX1 TIM8 CH1 request */
#define DMA_REQUEST_TIM8_CH2 51U /*!< DMAMUX1 TIM8 CH2 request */
#define DMA_REQUEST_TIM8_CH3 52U /*!< DMAMUX1 TIM8 CH3 request */
#define DMA_REQUEST_TIM8_CH4 53U /*!< DMAMUX1 TIM8 CH4 request */
#define DMA_REQUEST_TIM8_UP 54U /*!< DMAMUX1 TIM8 UP request */
#define DMA_REQUEST_TIM8_TRIG 55U /*!< DMAMUX1 TIM8 TRIG request */
#define DMA_REQUEST_TIM8_COM 56U /*!< DMAMUX1 TIM8 COM request */
#define DMA_REQUEST_TIM2_CH1 57U /*!< DMAMUX1 TIM2 CH1 request */
#define DMA_REQUEST_TIM2_CH2 58U /*!< DMAMUX1 TIM2 CH2 request */
#define DMA_REQUEST_TIM2_CH3 59U /*!< DMAMUX1 TIM2 CH3 request */
#define DMA_REQUEST_TIM2_CH4 60U /*!< DMAMUX1 TIM2 CH4 request */
#define DMA_REQUEST_TIM2_UP 61U /*!< DMAMUX1 TIM2 UP request */
#define DMA_REQUEST_TIM3_CH1 62U /*!< DMAMUX1 TIM3 CH1 request */
#define DMA_REQUEST_TIM3_CH2 63U /*!< DMAMUX1 TIM3 CH2 request */
#define DMA_REQUEST_TIM3_CH3 64U /*!< DMAMUX1 TIM3 CH3 request */
#define DMA_REQUEST_TIM3_CH4 65U /*!< DMAMUX1 TIM3 CH4 request */
#define DMA_REQUEST_TIM3_UP 66U /*!< DMAMUX1 TIM3 UP request */
#define DMA_REQUEST_TIM3_TRIG 67U /*!< DMAMUX1 TIM3 TRIG request */
#define DMA_REQUEST_TIM4_CH1 68U /*!< DMAMUX1 TIM4 CH1 request */
#define DMA_REQUEST_TIM4_CH2 69U /*!< DMAMUX1 TIM4 CH2 request */
#define DMA_REQUEST_TIM4_CH3 70U /*!< DMAMUX1 TIM4 CH3 request */
#define DMA_REQUEST_TIM4_CH4 71U /*!< DMAMUX1 TIM4 CH4 request */
#define DMA_REQUEST_TIM4_UP 72U /*!< DMAMUX1 TIM4 UP request */
#define DMA_REQUEST_TIM5_CH1 73U /*!< DMAMUX1 TIM5 CH1 request */
#define DMA_REQUEST_TIM5_CH2 74U /*!< DMAMUX1 TIM5 CH2 request */
#define DMA_REQUEST_TIM5_CH3 75U /*!< DMAMUX1 TIM5 CH3 request */
#define DMA_REQUEST_TIM5_CH4 76U /*!< DMAMUX1 TIM5 CH4 request */
#define DMA_REQUEST_TIM5_UP 77U /*!< DMAMUX1 TIM5 UP request */
#define DMA_REQUEST_TIM5_TRIG 78U /*!< DMAMUX1 TIM5 TRIG request */
#define DMA_REQUEST_TIM15_CH1 79U /*!< DMAMUX1 TIM15 CH1 request */
#define DMA_REQUEST_TIM15_UP 80U /*!< DMAMUX1 TIM15 UP request */
#define DMA_REQUEST_TIM15_TRIG 81U /*!< DMAMUX1 TIM15 TRIG request */
#define DMA_REQUEST_TIM15_COM 82U /*!< DMAMUX1 TIM15 COM request */
#define DMA_REQUEST_TIM16_CH1 83U /*!< DMAMUX1 TIM16 CH1 request */
#define DMA_REQUEST_TIM16_UP 84U /*!< DMAMUX1 TIM16 UP request */
#define DMA_REQUEST_TIM17_CH1 85U /*!< DMAMUX1 TIM17 CH1 request */
#define DMA_REQUEST_TIM17_UP 86U /*!< DMAMUX1 TIM17 UP request */
#define DMA_REQUEST_DFSDM1_FLT0 87U /*!< DMAMUX1 DFSDM1 Filter0 request */
#define DMA_REQUEST_DFSDM1_FLT1 88U /*!< DMAMUX1 DFSDM1 Filter1 request */
#define DMA_REQUEST_DCMI 91U /*!< DMAMUX1 DCMI request */
#define DMA_REQUEST_DCMI_PSSI 91U /*!< DMAMUX1 DCMI/PSSI request */
#define DMA_REQUEST_AES_IN 92U /*!< DMAMUX1 AES IN request */
#define DMA_REQUEST_AES_OUT 93U /*!< DMAMUX1 AES OUT request */
#define DMA_REQUEST_HASH_IN 94U /*!< DMAMUX1 HASH IN request */
#else
#define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */
#define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */
#define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */
#define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */
#define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */
#define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */
#define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */
#define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */
#define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */
#define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */
#define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */
#define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */
#define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */
#define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */
#define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */
#define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */
#define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */
#define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */
#define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */
#define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */
#define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */
#define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */
#define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */
#define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */
#define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */
#define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */
#define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */
#define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */
#define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */
#define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */
#define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */
#define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */
#define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */
#define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */
#define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */
#define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */
#define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */
#define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */
#define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */
#define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */
#define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */
#define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */
#define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */
#define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */
#define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */
#define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */
#define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */
#define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */
#define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */
#define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */
#define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */
#define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */
#define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */
#define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */
#define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */
#define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */
#define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */
#define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */
#define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */
#define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */
#define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */
#define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */
#define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */
#define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */
#define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */
#define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */
#define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */
#define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */
#define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */
#define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */
#define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */
#define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */
#define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */
#define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */
#define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */
#define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */
#define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */
#define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */
#define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */
#define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */
#define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */
#define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */
#define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */
#define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */
#define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */
#define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */
#define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */
#define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */
#endif /* STM32L4P5xx || STM32L4Q5xx */
#endif /* DMAMUX1 */
/**
* @}
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_mode DMA mode
* @{
*/
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
/**
* @}
*/
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
/**
* @}
*/
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
#define DMA_IT_TC DMA_CCR_TCIE
#define DMA_IT_HT DMA_CCR_HTIE
#define DMA_IT_TE DMA_CCR_TEIE
/**
* @}
*/
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
#define DMA_FLAG_GL1 DMA_ISR_GIF1
#define DMA_FLAG_TC1 DMA_ISR_TCIF1
#define DMA_FLAG_HT1 DMA_ISR_HTIF1
#define DMA_FLAG_TE1 DMA_ISR_TEIF1
#define DMA_FLAG_GL2 DMA_ISR_GIF2
#define DMA_FLAG_TC2 DMA_ISR_TCIF2
#define DMA_FLAG_HT2 DMA_ISR_HTIF2
#define DMA_FLAG_TE2 DMA_ISR_TEIF2
#define DMA_FLAG_GL3 DMA_ISR_GIF3
#define DMA_FLAG_TC3 DMA_ISR_TCIF3
#define DMA_FLAG_HT3 DMA_ISR_HTIF3
#define DMA_FLAG_TE3 DMA_ISR_TEIF3
#define DMA_FLAG_GL4 DMA_ISR_GIF4
#define DMA_FLAG_TC4 DMA_ISR_TCIF4
#define DMA_FLAG_HT4 DMA_ISR_HTIF4
#define DMA_FLAG_TE4 DMA_ISR_TEIF4
#define DMA_FLAG_GL5 DMA_ISR_GIF5
#define DMA_FLAG_TC5 DMA_ISR_TCIF5
#define DMA_FLAG_HT5 DMA_ISR_HTIF5
#define DMA_FLAG_TE5 DMA_ISR_TEIF5
#define DMA_FLAG_GL6 DMA_ISR_GIF6
#define DMA_FLAG_TC6 DMA_ISR_TCIF6
#define DMA_FLAG_HT6 DMA_ISR_HTIF6
#define DMA_FLAG_TE6 DMA_ISR_TEIF6
#define DMA_FLAG_GL7 DMA_ISR_GIF7
#define DMA_FLAG_TC7 DMA_ISR_TCIF7
#define DMA_FLAG_HT7 DMA_ISR_HTIF7
#define DMA_FLAG_TE7 DMA_ISR_TEIF7
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
/**
* @brief Return the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
DMA_ISR_GIF7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
/**
* @brief Enable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__ DMA handle
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/
#if defined(DMAMUX1)
/* Include DMA HAL Extension module */
#include "stm32l4xx_hal_dma_ex.h"
#endif /* DMAMUX1 */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
/** @addtogroup DMA_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @{
*/
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE))
#if !defined (DMAMUX1)
#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
((REQUEST) == DMA_REQUEST_1) || \
((REQUEST) == DMA_REQUEST_2) || \
((REQUEST) == DMA_REQUEST_3) || \
((REQUEST) == DMA_REQUEST_4) || \
((REQUEST) == DMA_REQUEST_5) || \
((REQUEST) == DMA_REQUEST_6) || \
((REQUEST) == DMA_REQUEST_7))
#endif
#if defined(DMAMUX1)
#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN)
#endif /* DMAMUX1 */
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_DMA_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DMA_EX_H
#define STM32L4xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(DMAMUX1)
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @{
*/
/**
* @brief HAL DMA Synchro definition
*/
/**
* @brief HAL DMAMUX Synchronization configuration structure definition
*/
typedef struct
{
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
This parameter can take the value ENABLE or DISABLE*/
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
This parameter can take the value ENABLE or DISABLE */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
} HAL_DMA_MuxSyncConfigTypeDef;
/**
* @brief HAL DMAMUX request generator parameters structure definition
*/
typedef struct
{
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @{
*/
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
* @{
*/
#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */
#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */
#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */
#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */
#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */
#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */
#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */
#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */
#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */
#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */
#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */
#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */
#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */
#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */
#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */
#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */
#define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */
#define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
* @{
*/
#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */
#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */
#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */
#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
* @{
*/
#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define HAL_DMAMUX1_REQ_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */
#define HAL_DMAMUX1_REQ_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */
#define HAL_DMAMUX1_REQ_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
* @{
*/
#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */
#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/* IO operation functions *****************************************************/
/** @addtogroup DMAEx_Exported_Functions_Group1
* @{
*/
/* ------------------------- REQUEST -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
/* -------------------------------------------------------------------------- */
/* ------------------------- SYNCHRO -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
/* -------------------------------------------------------------------------- */
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
* @brief DMAEx private macros
* @{
*/
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT)
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
((EVENT) == ENABLE))
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT)
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DMAMUX1 */
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_DMA_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_EXTI_H
#define STM32L4xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U,
HAL_EXTI_RISING_CB_ID = 0x01U,
HAL_EXTI_FALLING_CB_ID = 0x02U,
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#if defined(STM32L412xx) || defined(STM32L422xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L412xx || STM32L422xx */
#if defined(STM32L431xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L431xx */
#if defined(STM32L432xx) || defined(STM32L442xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L432xx || STM32L442xx */
#if defined(STM32L433xx) || defined(STM32L443xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L433xx || STM32L443xx */
#if defined(STM32L451xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
#endif /* STM32L451xx */
#if defined(STM32L452xx) || defined(STM32L462xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_RESERVED | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
#endif /* STM32L452xx || STM32L462xx */
#if defined(STM32L471xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L471xx */
#if defined(STM32L475xx) || defined(STM32L485xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L475xx || STM32L485xx */
#if defined(STM32L476xx) || defined(STM32L486xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_40 (EXTI_RESERVED | EXTI_REG2 | 0x08u)
#endif /* STM32L476xx || STM32L486xx */
#if defined(STM32L496xx) || defined(STM32L4A6xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
#endif /* STM32L496xx || STM32L4A6xx */
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | EXTI_EVENT | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x10u)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | EXTI_EVENT | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Cu)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Eu)
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | EXTI_EVENT | 0x1Fu)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x00u)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x03u)
#define EXTI_LINE_36 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x04u)
#define EXTI_LINE_37 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | EXTI_EVENT | 0x06u)
#define EXTI_LINE_39 (EXTI_RESERVED | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | EXTI_EVENT | 0x08u)
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000u
#define EXTI_MODE_INTERRUPT 0x00000001u
#define EXTI_MODE_EVENT 0x00000002u
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
#define EXTI_GPIOD 0x00000003u
#define EXTI_GPIOE 0x00000004u
#define EXTI_GPIOF 0x00000005u
#define EXTI_GPIOG 0x00000006u
#define EXTI_GPIOH 0x00000007u
#define EXTI_GPIOI 0x00000008u
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24u
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Event presence definition
*/
#define EXTI_EVENT_PRESENCE_SHIFT 28u
#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16u
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define EXTI_PIN_MASK 0x0000001Fu
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#define EXTI_LINE_NB 41u
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#if defined(STM32L412xx) || defined(STM32L422xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L412xx || STM32L422xx */
#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L431xx || STM32L433xx || STM32L443xx */
#if defined(STM32L432xx) || defined(STM32L442xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L432xx || STM32L442xx */
#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L451xx || STM32L452xx || STM32L462xx */
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH))
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
#if defined(STM32L496xx) || defined(STM32L4A6xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI))
#endif /* STM32L496xx || STM32L4A6xx */
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI))
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_EXTI_H */

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Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h Normal file
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Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h Normal file
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/**
******************************************************************************
* @file stm32l4xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of FLASH HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_FLASH_EX_H
#define STM32L4xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#if defined (FLASH_CFGR_LVEN)
/** @addtogroup FLASHEx_Exported_Constants
* @{
*/
/** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration
* @{
*/
#define FLASH_LVE_PIN_CTRL 0x00000000U /*!< LVE FLASH pin controlled by power controller */
#define FLASH_LVE_PIN_FORCED FLASH_CFGR_LVEN /*!< LVE FLASH pin enforced to low (external SMPS used) */
/**
* @}
*/
/**
* @}
*/
#endif /* FLASH_CFGR_LVEN */
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/* Extended Program operation functions *************************************/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
/**
* @}
*/
#if defined (FLASH_CFGR_LVEN)
/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE);
/**
* @}
*/
#endif /* FLASH_CFGR_LVEN */
/**
* @}
*/
/* Private function ----------------------------------------------------------*/
/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions
* @{
*/
void FLASH_PageErase(uint32_t Page, uint32_t Banks);
void FLASH_FlushCaches(void);
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/**
@cond 0
*/
#if defined (FLASH_CFGR_LVEN)
#define IS_FLASH_LVE_PIN(CFG) (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED))
#endif /* FLASH_CFGR_LVEN */
/**
@endcond
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_FLASH_EX_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_FLASH_RAMFUNC_H
#define STM32L4xx_FLASH_RAMFUNC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH_RAMFUNC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions
* @{
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
* @{
*/
/* Peripheral Control functions ************************************************/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_FLASH_RAMFUNC_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_GPIO_H
#define STM32L4xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0x00WX00YZ
* - W : EXTI trigger detection on 3 bits
* - X : EXTI mode (IT or Event) on 2 bits
* - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_ANALOG_ADC_CONTROL (MODE_ANALOG | 0x8uL) /*!< Analog Mode for ADC conversion (0x0000000Bu)*/
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE_Pos 0u
#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
#define MODE_AF (0x2uL << GPIO_MODE_Pos)
#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
#define OUTPUT_TYPE_Pos 4u
#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
#define EXTI_MODE_Pos 16u
#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
#define TRIGGER_MODE_Pos 20u
#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
/**
* @}
*/
/** @addtogroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_AF_PP) ||\
((__MODE__) == GPIO_MODE_AF_OD) ||\
((__MODE__) == GPIO_MODE_IT_RISING) ||\
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_ANALOG) ||\
((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
/**
* @}
*/
/* Include GPIO HAL Extended module */
#include "stm32l4xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_GPIO_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_I2C_H
#define STM32L4xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization section
in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
mode is selected.
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
__IO uint32_t Devaddress; /*!< I2C Target device address */
__IO uint32_t Memaddress; /*!< I2C Target memory address */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
/*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
#include "stm32l4xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
>> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
>> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
(uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32l4xx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_I2C_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_i2c_ex.h
* @author MCD Application Team
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_I2C_EX_H
#define STM32L4xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#else
#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */
#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(SYSCFG_CFGR1_I2C2_FMP)
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#else
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
#endif /* SYSCFG_CFGR1_I2C2_FMP */
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
#endif /* SYSCFG_CFGR1_I2C4_FMP */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_I2C_EX_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_pwr.h
* @author MCD Application Team
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_PWR_H
#define STM32L4xx_HAL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level. */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode. */
}PWR_PVDTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */
#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */
#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */
#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */
#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */
#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */
#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */
#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */
/**
* @}
*/
/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
/**
* @}
*/
/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
* @{
*/
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
* @}
*/
/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line
* @{
*/
#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWR_Exported_Macros PWR Exported Macros
* @{
*/
/** @brief Check whether or not a specific PWR flag is set.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
* was received from the WKUP pin 1.
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
* was received from the WKUP pin 2.
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
* was received from the WKUP pin 3.
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
* was received from the WKUP pin 4.
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
* was received from the WKUP pin 5.
* @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
* entered StandBy mode.
* @arg @ref PWR_FLAG_EXT_SMPS External SMPS Ready Flag. When available on device, indicates
* that external switch can be closed to connect to the external SMPS, when the Range 2
* of internal regulator is ready.
* @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
* the internal wakeup line.
* @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
* low-power regulator is ready.
* @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
* regulator is ready in main mode or is in low-power mode.
* @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
* in the selected voltage range or is still changing to the required voltage level.
* @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
* below or above the selected PVD threshold.
* @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
* is below or above PVM1 threshold (applicable when USB feature is supported).
@if STM32L486xx
* @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
* is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
@endif
* @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
* is below or above PVM3 threshold.
* @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
* is below or above PVM4 threshold.
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\
(PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
(PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
/** @brief Clear a specific PWR flag.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
* was received from the WKUP pin 1.
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
* was received from the WKUP pin 2.
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
* was received from the WKUP pin 3.
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
* was received from the WKUP pin 4.
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
* was received from the WKUP pin 5.
* @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
* @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
* entered Standby mode.
* @retval None
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
(PWR->SCR = (__FLAG__)) :\
(PWR->SCR = (1U << ((__FLAG__) & 31U))) )
/**
* @brief Enable the PVD Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Event Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
/**
* @brief Disable the PVD Event Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
/**
* @brief Check whether or not the PVD EXTI interrupt flag is set.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
/**
* @brief Clear the PVD EXTI interrupt flag.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWR_Private_Macros PWR Private Macros
* @{
*/
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\
((MODE) == PWR_PVD_MODE_IT_RISING) ||\
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
/**
* @}
*/
/* Include PWR HAL Extended module */
#include "stm32l4xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
/* WakeUp pins configuration functions ****************************************/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low Power modes configuration functions ************************************/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_PVDCallback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_PWR_H */

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/**
******************************************************************************
* @file stm32l4xx_hal_pwr_ex.h
* @author MCD Application Team
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_PWR_EX_H
#define STM32L4xx_HAL_PWR_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup PWREx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
* @{
*/
/**
* @brief PWR PVM configuration structure definition
*/
typedef struct
{
uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
This parameter can be a value of @ref PWREx_PVM_Type.
@arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
@if STM32L486xx
@arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device).
@endif
@arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
@arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWREx_PVM_Mode. */
}PWR_PVMTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
* @{
*/
/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
* @{
*/
#define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */
/**
* @}
*/
/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
* @{
*/
#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
/**
* @}
*/
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
* @{
*/
#if defined(PWR_CR2_PVME1)
#define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_PVM_2 PWR_CR2_PVME2 /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
#endif /* PWR_CR2_PVME2 */
#define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
#define PWR_PVM_4 PWR_CR2_PVME4 /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V */
/**
* @}
*/
/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
* @{
*/
#define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
#define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
* @{
*/
#if defined(PWR_CR5_R1MODE)
#define PWR_REGULATOR_VOLTAGE_SCALE1_BOOST ((uint32_t)0x00000000) /*!< Voltage scaling range 1 boost mode */
#endif
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 normal mode */
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
* @{
*/
#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
* @{
*/
#define PWR_BATTERY_CHARGING_DISABLE ((uint32_t)0x00000000)
#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
/**
* @}
*/
/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
* @{
*/
#define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
#define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
#define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
#define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
#define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
#define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
#define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
#define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
#define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
#define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
#define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
#define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
#define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
#define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 13 */
#define PWR_GPIO_BIT_14 PWR_PDCRA_PA14 /*!< GPIO port I/O pin 14 */
#define PWR_GPIO_BIT_15 PWR_PUCRA_PA15 /*!< GPIO port I/O pin 15 */
/**
* @}
*/
/** @defgroup PWREx_GPIO GPIO port
* @{
*/
#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */
#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */
#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */
#if defined(GPIOD_BASE)
#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */
#endif
#if defined(GPIOE_BASE)
#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */
#endif
#if defined(GPIOF_BASE)
#define PWR_GPIO_F 0x00000005U /*!< GPIO port F */
#endif
#if defined(GPIOG_BASE)
#define PWR_GPIO_G 0x00000006U /*!< GPIO port G */
#endif
#define PWR_GPIO_H 0x00000007U /*!< GPIO port H */
#if defined(GPIOI_BASE)
#define PWR_GPIO_I 0x00000008U /*!< GPIO port I */
#endif
/**
* @}
*/
/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
* @{
*/
#if defined(PWR_CR2_PVME1)
#define PWR_EXTI_LINE_PVM1 ((uint32_t)0x00000008) /*!< External interrupt line 35 Connected to the PVM1 EXTI Line */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_EXTI_LINE_PVM2 ((uint32_t)0x00000010) /*!< External interrupt line 36 Connected to the PVM2 EXTI Line */
#endif /* PWR_CR2_PVME2 */
#define PWR_EXTI_LINE_PVM3 ((uint32_t)0x00000020) /*!< External interrupt line 37 Connected to the PVM3 EXTI Line */
#define PWR_EXTI_LINE_PVM4 ((uint32_t)0x00000040) /*!< External interrupt line 38 Connected to the PVM4 EXTI Line */
/**
* @}
*/
/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
* @{
*/
#if defined(PWR_CR2_PVME1)
#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008) /*!< Event line 35 Connected to the PVM1 EXTI Line */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010) /*!< Event line 36 Connected to the PVM2 EXTI Line */
#endif /* PWR_CR2_PVME2 */
#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020) /*!< Event line 37 Connected to the PVM3 EXTI Line */
#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040) /*!< Event line 38 Connected to the PVM4 EXTI Line */
/**
* @}
*/
/** @defgroup PWREx_Flag PWR Status Flags
* Elements values convention: 0000 0000 0XXY YYYYb
* - Y YYYY : Flag position in the XX register (5 bits)
* - XX : Status register (2 bits)
* - 01: SR1 register
* - 10: SR2 register
* The only exception is PWR_FLAG_WU, encompassing all
* wake-up flags and set to PWR_SR1_WUF.
* @{
*/
#define PWR_FLAG_WUF1 ((uint32_t)0x0020) /*!< Wakeup event on wakeup pin 1 */
#define PWR_FLAG_WUF2 ((uint32_t)0x0021) /*!< Wakeup event on wakeup pin 2 */
#define PWR_FLAG_WUF3 ((uint32_t)0x0022) /*!< Wakeup event on wakeup pin 3 */
#define PWR_FLAG_WUF4 ((uint32_t)0x0023) /*!< Wakeup event on wakeup pin 4 */
#define PWR_FLAG_WUF5 ((uint32_t)0x0024) /*!< Wakeup event on wakeup pin 5 */
#define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
#define PWR_FLAG_SB ((uint32_t)0x0028) /*!< Standby flag */
#if defined(PWR_SR1_EXT_SMPS_RDY)
#define PWR_FLAG_EXT_SMPS ((uint32_t)0x002D) /*!< Switching to external SMPS ready flag */
#endif /* PWR_SR1_EXT_SMPS_RDY */
#define PWR_FLAG_WUFI ((uint32_t)0x002F) /*!< Wakeup on internal wakeup line */
#define PWR_FLAG_REGLPS ((uint32_t)0x0048) /*!< Low-power regulator start flag */
#define PWR_FLAG_REGLPF ((uint32_t)0x0049) /*!< Low-power regulator flag */
#define PWR_FLAG_VOSF ((uint32_t)0x004A) /*!< Voltage scaling flag */
#define PWR_FLAG_PVDO ((uint32_t)0x004B) /*!< Power Voltage Detector output flag */
#if defined(PWR_CR2_PVME1)
#define PWR_FLAG_PVMO1 ((uint32_t)0x004C) /*!< Power Voltage Monitoring 1 output flag */
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
#define PWR_FLAG_PVMO2 ((uint32_t)0x004D) /*!< Power Voltage Monitoring 2 output flag */
#endif /* PWR_CR2_PVME2 */
#define PWR_FLAG_PVMO3 ((uint32_t)0x004E) /*!< Power Voltage Monitoring 3 output flag */
#define PWR_FLAG_PVMO4 ((uint32_t)0x004F) /*!< Power Voltage Monitoring 4 output flag */
/**
* @}
*/
/** @defgroup PWREx_SRAM2_Retention PWR SRAM2 Retention in Standby mode
* @{
*/
#define PWR_NO_SRAM2_RETENTION ((uint32_t)0x00000000) /*!< SRAM2 is powered off in Standby mode (SRAM2 content is lost) */
#if defined(PWR_CR3_RRS_1)
#define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0 /*!< Full SRAM2 is powered by the low-power regulator in Standby mode */
#define PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1 /*!< Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode */
#else
#define PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS /*!< Full SRAM2 is powered by the low-power regulator in Standby mode */
#endif /* PWR_CR3_RRS_1 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
* @{
*/
#if defined(PWR_CR2_PVME1)
/**
* @brief Enable the PVM1 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Disable the PVM1 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Enable the PVM1 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
/**
* @brief Disable the PVM1 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
/**
* @brief Enable the PVM1 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Disable the PVM1 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Enable the PVM1 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief Disable the PVM1 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
/**
* @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
/**
* @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
* @retval EXTI PVM1 Line Status.
*/
#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
/**
* @brief Clear the PVM1 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
/**
* @brief Enable the PVM2 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Disable the PVM2 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Enable the PVM2 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
/**
* @brief Disable the PVM2 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
/**
* @brief Enable the PVM2 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Disable the PVM2 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Enable the PVM2 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief Disable the PVM2 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
/**
* @brief PVM2 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
/**
* @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
* @retval EXTI PVM2 Line Status.
*/
#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
/**
* @brief Clear the PVM2 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
#endif /* PWR_CR2_PVME2 */
/**
* @brief Enable the PVM3 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Disable the PVM3 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Enable the PVM3 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
/**
* @brief Disable the PVM3 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
/**
* @brief Enable the PVM3 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Disable the PVM3 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Enable the PVM3 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Disable the PVM3 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
/**
* @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
/**
* @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
* @retval EXTI PVM3 Line Status.
*/
#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
/**
* @brief Clear the PVM3 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
/**
* @brief Enable the PVM4 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Disable the PVM4 Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Enable the PVM4 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
/**
* @brief Disable the PVM4 Event Line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
/**
* @brief Enable the PVM4 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Disable the PVM4 Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Enable the PVM4 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Disable the PVM4 Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
/**
* @brief PVM4 EXTI line configuration: set rising & falling edge trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
/**
* @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
* @retval EXTI PVM4 Line Status.
*/
#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
/**
* @brief Clear the PVM4 EXTI flag.
* @retval None
*/
#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
/**
* @brief Configure the main internal regulator output voltage.
* @param __REGULATOR__ specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption.
* This parameter can be one of the following values:
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
* typical output voltage at 1.2 V,
* system frequency up to 80 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
* typical output voltage at 1.0 V,
* system frequency up to 26 MHz.
* @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
* whether or not VOSF flag is cleared when moving from range 2 to range 1. User
* may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
* @retval None
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
__IO uint32_t tmpreg; \
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
UNUSED(tmpreg); \
} while(0)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
* @{
*/
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN3) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN5) || \
((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
((PIN) == PWR_WAKEUP_PIN3_LOW) || \
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
((PIN) == PWR_WAKEUP_PIN5_LOW))
#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
((TYPE) == PWR_PVM_2) ||\
((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#elif defined (STM32L471xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#endif
#if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
((TYPE) == PWR_PVM_4))
#endif
#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
((MODE) == PWR_PVM_MODE_IT_RISING) ||\
((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
#if defined(PWR_CR5_R1MODE)
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
#else
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
#endif
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
#if defined (STM32L412xx) || defined (STM32L422xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \
defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L432xx) || defined (STM32L442xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_F) ||\
((GPIO) == PWR_GPIO_G) ||\
((GPIO) == PWR_GPIO_H))
#elif defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_F) ||\
((GPIO) == PWR_GPIO_G) ||\
((GPIO) == PWR_GPIO_H) ||\
((GPIO) == PWR_GPIO_I))
#endif
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx)
#define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\
((SRAM2) == PWR_FULL_SRAM2_RETENTION) ||\
((SRAM2) == PWR_4KBYTES_SRAM2_RETENTION))
#else
#define IS_PWR_SRAM2_RETENTION(SRAM2) (((SRAM2) == PWR_NO_SRAM2_RETENTION) ||\
((SRAM2) == PWR_FULL_SRAM2_RETENTION))
#endif
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
* @{
*/
/* Peripheral Control functions **********************************************/
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
void HAL_PWREx_DisableBatteryCharging(void);
#if defined(PWR_CR2_USV)
void HAL_PWREx_EnableVddUSB(void);
void HAL_PWREx_DisableVddUSB(void);
#endif /* PWR_CR2_USV */
#if defined(PWR_CR2_IOSV)
void HAL_PWREx_EnableVddIO2(void);
void HAL_PWREx_DisableVddIO2(void);
#endif /* PWR_CR2_IOSV */
void HAL_PWREx_EnableInternalWakeUpLine(void);
void HAL_PWREx_DisableInternalWakeUpLine(void);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
void HAL_PWREx_EnablePullUpPullDownConfig(void);
void HAL_PWREx_DisablePullUpPullDownConfig(void);
void HAL_PWREx_EnableSRAM2ContentRetention(void);
void HAL_PWREx_DisableSRAM2ContentRetention(void);
HAL_StatusTypeDef HAL_PWREx_SetSRAM2ContentRetention(uint32_t SRAM2Size);
#if defined(PWR_CR1_RRSTP)
void HAL_PWREx_EnableSRAM3ContentRetention(void);
void HAL_PWREx_DisableSRAM3ContentRetention(void);
#endif /* PWR_CR1_RRSTP */
#if defined(PWR_CR3_DSIPDEN)
void HAL_PWREx_EnableDSIPinsPDActivation(void);
void HAL_PWREx_DisableDSIPinsPDActivation(void);
#endif /* PWR_CR3_DSIPDEN */
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_EnablePVM1(void);
void HAL_PWREx_DisablePVM1(void);
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
void HAL_PWREx_EnablePVM2(void);
void HAL_PWREx_DisablePVM2(void);
#endif /* PWR_CR2_PVME2 */
void HAL_PWREx_EnablePVM3(void);
void HAL_PWREx_DisablePVM3(void);
void HAL_PWREx_EnablePVM4(void);
void HAL_PWREx_DisablePVM4(void);
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
#if defined(PWR_CR3_ENULP)
void HAL_PWREx_EnableBORPVD_ULP(void);
void HAL_PWREx_DisableBORPVD_ULP(void);
#endif /* PWR_CR3_ENULP */
#if defined(PWR_CR4_EXT_SMPS_ON)
void HAL_PWREx_EnableExtSMPS_0V95(void);
void HAL_PWREx_DisableExtSMPS_0V95(void);
#endif /* PWR_CR4_EXT_SMPS_ON */
/* Low Power modes configuration functions ************************************/
void HAL_PWREx_EnableLowPowerRunMode(void);
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSHUTDOWNMode(void);
void HAL_PWREx_PVD_PVM_IRQHandler(void);
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_PVM1Callback(void);
#endif /* PWR_CR2_PVME1 */
#if defined(PWR_CR2_PVME2)
void HAL_PWREx_PVM2Callback(void);
#endif /* PWR_CR2_PVME2 */
void HAL_PWREx_PVM3Callback(void);
void HAL_PWREx_PVM4Callback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_HAL_PWR_EX_H */

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/**
******************************************************************************
* @file stm32l4xx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) MPU API to configure and enable regions
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_LL_CORTEX_H
#define STM32L4xx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
/** @addtogroup STM32L4xx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
* @{
*/
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
* @{
*/
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
* @{
*/
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
* @{
*/
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
* @{
*/
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
* @{
*/
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
* @{
*/
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
{
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
else
{
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x0: revision 0)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Constant number
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
* @retval Value should be equal to 0xF for Cortex-M4 devices
*/
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xC24 for Cortex-M4
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EF_MPU MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param Options This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
{
/* Enable the MPU*/
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU*/
WRITE_REG(MPU->CTRL, 0U);
}
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
}
/**
* @brief Enable a MPU region
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Configure and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RASR XN LL_MPU_ConfigRegion\n
* MPU_RASR AP LL_MPU_ConfigRegion\n
* MPU_RASR S LL_MPU_ConfigRegion\n
* MPU_RASR C LL_MPU_ConfigRegion\n
* MPU_RASR B LL_MPU_ConfigRegion\n
* MPU_RASR SIZE LL_MPU_ConfigRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Address Value of region base address
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
}
/**
* @brief Disable a region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RASR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_LL_CORTEX_H */

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Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h Normal file
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/**
******************************************************************************
* @file stm32l4xx_ll_crs.h
* @author MCD Application Team
* @brief Header file of CRS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_LL_CRS_H
#define STM32L4xx_LL_CRS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
/** @addtogroup STM32L4xx_LL_Driver
* @{
*/
#if defined(CRS)
/** @defgroup CRS_LL CRS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
* @{
*/
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CRS_ReadReg function
* @{
*/
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
/**
* @}
*/
/** @defgroup CRS_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
* @{
*/
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
* @{
*/
#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
* @{
*/
#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
* @{
*/
#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
* @{
*/
/**
* @brief Reset value of the RELOAD field
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
*/
#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
/**
* @brief Reset value of Frequency error limit.
*/
#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
/**
* @brief Reset value of the HSI48 Calibration field
* @note The default value is 64 for STM32L412xx/L422xx, 32 otherwise, which corresponds
* to the middle of the trimming interval.
* The trimming step is around 67 kHz between two consecutive TRIM steps.
* A higher TRIM value corresponds to a higher output frequency
*/
#if defined (STM32L412xx) || defined (STM32L422xx)
#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)64U)
#else
#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)32U)
#endif
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
* @{
*/
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
* @{
*/
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between
* the target frequency and the frequency of the synchronization source after
* prescaling. It is then decreased by one in order to reach the expected
* synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval Reload value (in Hz)
*/
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
* @{
*/
/** @defgroup CRS_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Frequency error counter
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
{
SET_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Disable Frequency error counter
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Check if Frequency error counter is enabled or not
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
{
return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
}
/**
* @brief Enable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
{
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Disable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Check if Automatic trimming is enabled or not
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
{
return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
}
/**
* @brief Set HSI48 oscillator smooth trimming
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
* @param Value a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
}
/**
* @brief Get HSI48 oscillator smooth trimming
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
* @retval a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
*/
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
{
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
}
/**
* @brief Set counter reload value
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
}
/**
* @brief Get counter reload value
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
}
/**
* @brief Set frequency error limit
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
* @param Value a number between Min_Data = 0 and Max_Data = 255
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
}
/**
* @brief Get frequency error limit
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
* @retval A number between Min_Data = 0 and Max_Data = 255
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
}
/**
* @brief Set division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
* @param Divider This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
}
/**
* @brief Get division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
}
/**
* @brief Set SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
}
/**
* @brief Get SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
}
/**
* @brief Set input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
}
/**
* @brief Get input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
}
/**
* @brief Configure CRS for the synchronization
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
* CFGR FELIM LL_CRS_ConfigSynchronization\n
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
* @param Settings This parameter can be a combination of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
* or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
MODIFY_REG(CRS->CFGR,
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
* @{
*/
/**
* @brief Generate software SYNC event
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
}
/**
* @brief Get the frequency error direction latched in the time of the last
* SYNC event
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
}
/**
* @brief Get the frequency error counter value latched in the time of the last SYNC event
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if SYNC event OK signal occurred or not
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
}
/**
* @brief Check if SYNC warning signal occurred or not
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
}
/**
* @brief Check if Synchronization or trimming error signal occurred or not
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
}
/**
* @brief Check if Expected SYNC signal occurred or not
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
}
/**
* @brief Check if SYNC error signal occurred or not
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
}
/**
* @brief Check if SYNC missed error signal occurred or not
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
}
/**
* @brief Check if Trimming overflow or underflow occurred or not
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
{
return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
}
/**
* @brief Clear the SYNC event OK flag
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
}
/**
* @brief Clear the SYNC warning flag
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
}
/**
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
* the ERR flag
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
}
/**
* @brief Clear Expected SYNC flag
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Disable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Check if SYNC event OK interrupt is enabled or not
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
{
return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
}
/**
* @brief Enable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Disable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Check if SYNC warning interrupt is enabled or not
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
{
return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
}
/**
* @brief Enable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
{
SET_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Disable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Check if Synchronization or trimming error interrupt is enabled or not
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
{
return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
}
/**
* @brief Enable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Disable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Check if Expected SYNC interrupt is enabled or not
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
{
return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRS_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRS) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_LL_CRS_H */

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/**
******************************************************************************
* @file stm32l4xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_LL_UTILS_H
#define STM32L4xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h"
/** @addtogroup STM32L4xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @brief Package data register base address
*/
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 8 and Max_Data = 86
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t PLLR; /*!< Division for the main system clock.
This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
* @{
*/
#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
#define LL_UTILS_PACKAGETYPE_BGA132 0x00000003U /*!< BGA132 package type */
#define LL_UTILS_PACKAGETYPE_LQFP144_CSP72 0x00000004U /*!< LQFP144, WLCSP81 or WLCSP72 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */
#define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169_CSP115 0x00000010U /*!< UFBGA169 or WLCSP115 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100_DSI 0x00000012U /*!< LQFP100 with DSI package type */
#define LL_UTILS_PACKAGETYPE_WLCSP144_DSI 0x00000013U /*!< WLCSP144 with DSI package type */
#define LL_UTILS_PACKAGETYPE_UFBGA144_DSI 0x00000013U /*!< UFBGA144 with DSI package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169_DSI 0x00000014U /*!< UFBGA169 with DSI package type */
#define LL_UTILS_PACKAGETYPE_LQFP144_DSI 0x00000015U /*!< LQFP144 with DSI package type */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
}
/**
* @brief Get Package type
* @retval Returned value can be one of the following values:
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_BGA132 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_DSI (*)
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_DSI (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_DSI (*)
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_DSI (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_DSI (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Frequency of Ticks (Hz)
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L4xx_LL_UTILS_H */

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This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the BSD-3-Clause license shall apply.
You may obtain a copy of the BSD-3-Clause at:
https://opensource.org/licenses/BSD-3-Clause

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/**
******************************************************************************
* @file stm32l4xx_hal.c
* @author MCD Application Team
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup HAL HAL
* @brief HAL module driver
* @{
*/
#ifdef HAL_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32L4xx HAL Driver version number
*/
#define STM32L4XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L4XX_HAL_VERSION_SUB1 (0x0DU) /*!< [23:16] sub1 version */
#define STM32L4XX_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
#define STM32L4XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L4XX_HAL_VERSION ((STM32L4XX_HAL_VERSION_MAIN << 24U)\
|(STM32L4XX_HAL_VERSION_SUB1 << 16U)\
|(STM32L4XX_HAL_VERSION_SUB2 << 8U)\
|(STM32L4XX_HAL_VERSION_RC))
#if defined(VREFBUF)
#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */
#endif /* VREFBUF */
/* ------------ SYSCFG registers bit address in the alias region ------------ */
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- MEMRMP Register ---*/
/* Alias word address of FB_MODE bit */
#define MEMRMP_OFFSET SYSCFG_OFFSET
#define FB_MODE_BitNumber 8U
#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (FB_MODE_BitNumber * 4U))
/* --- SCSR Register ---*/
/* Alias word address of SRAM2ER bit */
#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18U)
#define BRER_BitNumber 0U
#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32U) + (BRER_BitNumber * 4U))
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported variables --------------------------------------------------------*/
/** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the Flash interface, the NVIC allocation and initial time base
clock configuration.
(+) De-initialize common part of the HAL.
(+) Configure the time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
/**
* @brief Configure the Flash prefetch, the Instruction and Data caches,
* the time base source, NVIC and any required global low level hardware
* by calling the HAL_MspInit() callback function to be optionally defined in user file
* stm32l4xx_hal_msp.c.
*
* @note HAL_Init() function is called at the beginning of program after reset and before
* the clock configuration.
*
* @note In the default implementation the System Timer (Systick) is used as source of time base.
* The Systick configuration is based on MSI clock, as MSI is the clock
* used after a system Reset and the NVIC configuration is set to Priority group 4.
* Once done, time base tick starts incrementing: the tick variable counter is incremented
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
HAL_StatusTypeDef status = HAL_OK;
/* Configure Flash prefetch, Instruction cache, Data cache */
/* Default configuration at reset is: */
/* - Prefetch disabled */
/* - Instruction cache enabled */
/* - Data cache enabled */
#if (INSTRUCTION_CACHE_ENABLE == 0)
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE == 0)
__HAL_FLASH_DATA_CACHE_DISABLE();
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
status = HAL_ERROR;
}
else
{
/* Init the low level hardware */
HAL_MspInit();
}
/* Return function status */
return status;
}
/**
* @brief De-initialize common part of the HAL and stop the source of time base.
* @note This function is optional.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
__HAL_RCC_APB1_FORCE_RESET();
__HAL_RCC_APB1_RELEASE_RESET();
__HAL_RCC_APB2_FORCE_RESET();
__HAL_RCC_APB2_RELEASE_RESET();
__HAL_RCC_AHB1_FORCE_RESET();
__HAL_RCC_AHB1_RELEASE_RESET();
__HAL_RCC_AHB2_FORCE_RESET();
__HAL_RCC_AHB2_RELEASE_RESET();
__HAL_RCC_AHB3_FORCE_RESET();
__HAL_RCC_AHB3_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function configures the source of the time base:
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
@endverbatim
* @{
*/
/**
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += (uint32_t)uwTickFreq;
}
/**
* @brief Provide a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
}
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @param Freq tick frequency
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_TickFreqTypeDef prevTickFreq;
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}
return status;
}
/**
* @brief Return tick frequency.
* @retval Tick frequency.
* Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait += (uint32_t)uwTickFreq;
}
while ((HAL_GetTick() - tickstart) < wait)
{
}
}
/**
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Return the HAL revision.
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
return STM32L4XX_HAL_VERSION;
}
/**
* @brief Return the device revision identifier.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
}
/**
* @brief Return the device identifier.
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
{
return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
}
/**
* @brief Return the first word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw0(void)
{
return(READ_REG(*((uint32_t *)UID_BASE)));
}
/**
* @brief Return the second word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw1(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
* @brief Return the third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw2(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
* @brief HAL Debug functions
*
@verbatim
===============================================================================
##### HAL Debug functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief Enable the Debug Module during SLEEP mode.
* @retval None
*/
void HAL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode.
* @retval None
*/
void HAL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
* @brief HAL SYSCFG configuration functions
*
@verbatim
===============================================================================
##### HAL SYSCFG configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start a hardware SRAM2 erase operation
(+) Enable/Disable the Internal FLASH Bank Swapping
(+) Configure the Voltage reference buffer
(+) Enable/Disable the Voltage reference buffer
(+) Enable/Disable the I/O analog switch voltage booster
@endverbatim
* @{
*/
/**
* @brief Start a hardware SRAM2 erase operation.
* @note As long as SRAM2 is not erased the SRAM2ER bit will be set.
* This bit is automatically reset at the end of the SRAM2 erase operation.
* @retval None
*/
void HAL_SYSCFG_SRAM2Erase(void)
{
/* unlock the write protection of the SRAM2ER bit */
SYSCFG->SKR = 0xCA;
SYSCFG->SKR = 0x53;
/* Starts a hardware SRAM2 erase operation*/
*(__IO uint32_t *) SCSR_SRAM2ER_BB = 0x00000001UL;
}
/**
* @brief Enable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32L4xx devices.
*
* @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
*
* @retval None
*/
void HAL_SYSCFG_EnableMemorySwappingBank(void)
{
*(__IO uint32_t *)FB_MODE_BB = 0x00000001UL;
}
/**
* @brief Disable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32L4xx devices.
*
* @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
* and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
*
* @retval None
*/
void HAL_SYSCFG_DisableMemorySwappingBank(void)
{
*(__IO uint32_t *)FB_MODE_BB = 0x00000000UL;
}
#if defined(VREFBUF)
/**
* @brief Configure the internal voltage reference buffer voltage scale.
* @param VoltageScaling specifies the output voltage to achieve
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
* This requires VDDA equal to or higher than 2.4 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
* This requires VDDA equal to or higher than 2.8 V.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
}
/**
* @brief Configure the internal voltage reference buffer high impedance mode.
* @param Mode specifies the high impedance mode
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
}
/**
* @brief Tune the Internal Voltage Reference buffer (VREFBUF).
* @retval None
*/
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
}
/**
* @brief Enable the Internal Voltage Reference buffer (VREFBUF).
* @retval HAL_OK/HAL_TIMEOUT
*/
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
{
uint32_t tickstart;
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait for VRR bit */
while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)
{
if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Disable the Internal Voltage Reference buffer (VREFBUF).
*
* @retval None
*/
void HAL_SYSCFG_DisableVREFBUF(void)
{
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
#endif /* VREFBUF */
/**
* @brief Enable the I/O analog switch voltage booster
*
* @retval None
*/
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Disable the I/O analog switch voltage booster
*
* @retval None
*/
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32l4xx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and Configuration functions
* + Peripheral Control functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M4 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest pre-emption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure SysTick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32l4xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
@endverbatim
******************************************************************************
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
==========================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
==========================================================================================================================
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
| | | 4 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
| | | 3 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bit for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bit for subpriority
==========================================================================================================================
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
SysTick functionalities
@endverbatim
* @{
*/
/**
* @brief Set the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
* 0 bit for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Set the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @param PreemptPriority: The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup = 0x00;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enable a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disable a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiate a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
/**
* @brief Get the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Get the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
* 0 bit for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Set Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Get Pending Interrupt (read the pending register in the NVIC
* and return the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clear the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Get active interrupt (read the active register in NVIC and return the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configure the SysTick clock source.
* @param CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
{
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}
else
{
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
}
}
/**
* @brief Handle SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
#if (__MPU_PRESENT == 1)
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged accessto the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Disable the MPU.
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0;
}
/**
* @brief Enable the MPU Region.
* @retval None
*/
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Enable the Region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Disable the MPU Region.
* @retval None
*/
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
/* Set the Region number */
MPU->RNR = RegionNumber;
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Initialize and configure the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
/* Disable the Region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
/* Apply configuration */
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32l4xx_hal_dma_ex.c
* @author MCD Application Team
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
* + Extended features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
(+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
(exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
the AHB memory port on the fly (DMA_CM0ARx or DMA_CM1ARx) when the channel is enabled.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
#if defined(DMAMUX1)
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private Constants ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
* @{
*/
/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
* @brief Extended features functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator.
@endverbatim
* @{
*/
/**
* @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
/*Check if the DMA state is ready */
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
MODIFY_REG(hdma->DMAmuxChannel->CCR, \
(~DMAMUX_CxCR_DMAREQ_ID), \
((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
/* Process UnLocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
/*DMA State not Ready*/
return HAL_ERROR;
}
}
/**
* @brief Configure the DMAMUX request generator block used by the given DMA channel (instance).
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
* contains the request generator parameters.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Set the request generator new parameters */
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \
pRequestGeneratorConfig->Polarity;
/* Process UnLocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Enable the DMAMUX request generator block used by the given DMA channel (instance).
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Enable the request generator*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Disable the DMAMUX request generator block used by the given DMA channel (instance).
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* check if the DMA state is ready
and DMA is using a DMAMUX request generator block
*/
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
{
/* Disable the request generator*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handles DMAMUX interrupt request.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA channel.
* @retval None
*/
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
{
/* Check for DMAMUX Synchronization overrun */
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
{
/* Disable the synchro overrun interrupt */
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
if (hdma->DMAmuxRequestGen != 0)
{
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
{
/* Disable the request gen overrun interrupt */
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
#endif /* DMAMUX1 */

638
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c Normal file
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@ -0,0 +1,638 @@
/**
******************************************************************************
* @file stm32l4xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two different
interrupts pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rule:
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
* of bounds [0,3] in following API :
* HAL_EXTI_SetConfigLine
* HAL_EXTI_GetConfigLine
* HAL_EXTI_ClearConfigLine
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between MCU IMR/EMR registers */
#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between MCU Rising/Falling configuration registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* Compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
/* Configure interrupt mode : read current mode */
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
/* Configure event mode : read current mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* Compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Get core mode : interrupt */
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get event mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* Get default Trigger and GPIOSel configuration */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
/* Get falling configuration */
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
}
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear event mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->PendingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
{
hexti->PendingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Get pending bit */
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Prevent unused argument(s) compilation warning */
UNUSED(Edge);
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending register address */
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c Normal file
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@ -0,0 +1,764 @@
/**
******************************************************************************
* @file stm32l4xx_hal_flash.c
* @author MCD Application Team
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Peripheral Errors functions
*
@verbatim
==============================================================================
##### FLASH peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
and the read and write protection mechanisms.
[..] The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
[..] The FLASH main features are:
(+) Flash memory read operations
(+) Flash memory program/erase operations
(+) Read / write protections
(+) Option bytes programming
(+) Prefetch on I-Code
(+) 32 cache lines of 4*64 bits on I-Code
(+) 8 cache lines of 4*64 bits on D-Code
(+) Error code correction (ECC) : Data in flash are 72-bits word
(8 bits added per double word)
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32L4xx devices.
(#) Flash Memory IO Programming functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Program functions: double word and fast program (full row programming)
(++) There Two modes of programming :
(+++) Polling mode using HAL_FLASH_Program() function
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
(#) Interrupts and flags management functions :
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
(++) Callback functions are called when the flash operations are finished :
HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
HAL_FLASH_OperationErrorCallback()
(++) Get error flag status by calling HAL_GetError()
(#) Option bytes management functions :
(++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
HAL_FLASH_OB_Lock() functions
(++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
In this case, a reset is generated
[..]
In addition to these functions, this driver includes a set of macros allowing
to handle the following operations:
(+) Set the latency
(+) Enable/Disable the prefetch buffer
(+) Enable/Disable the Instruction cache and the Data cache
(+) Reset the Instruction cache and the Data cache
(+) Enable/Disable the Flash power-down during low-power run and sleep modes
(+) Enable/Disable the Flash interrupts
(+) Monitor the Flash flags status
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64
#else
#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32
#endif
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
/**
* @brief Variable used for Program/Erase sectors under interruption
*/
FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
.ErrorCode = HAL_FLASH_ERROR_NONE, \
.ProcedureOnGoing = FLASH_PROC_NONE, \
.Address = 0U, \
.Bank = FLASH_BANK_1, \
.Page = 0U, \
.NbPagesToErase = 0U, \
.CacheToReactivate = FLASH_CACHE_DISABLED};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
===============================================================================
##### Programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
program operations.
@endverbatim
* @{
*/
/**
* @brief Program double word or fast program of a row at a specified address.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed
* This parameter is the data for the double word program and the address where
* are stored the data for the row fast program
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status;
uint32_t prog_bit = 0;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Deactivate the data cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
}
if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
/* Program double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, Data);
prog_bit = FLASH_CR_PG;
}
else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
{
/* Fast program a 32 row double-word (64-bit) at a specified address */
FLASH_Program_Fast(Address, (uint32_t)Data);
/* If it is the last row, the bit will be cleared at the end of the operation */
if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
{
prog_bit = FLASH_CR_FSTPG;
}
}
else
{
/* Nothing to do */
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG or FSTPG Bit */
if (prog_bit != 0U)
{
CLEAR_BIT(FLASH->CR, prog_bit);
}
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches();
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
/**
* @brief Program double word or fast program of a row at a specified address with interrupt enabled.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed
* This parameter is the data for the double word program and the address where
* are stored the data for the row fast program
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Process Locked */
__HAL_LOCK(&pFlash);
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Deactivate the data cache if they are activated to avoid data misbehavior */
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
}
else
{
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
}
/* Set internal variables used by the IRQ handler */
if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
}
else
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
}
pFlash.Address = Address;
/* Enable End of Operation and Error interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
{
/* Program double-word (64-bit) at a specified address */
FLASH_Program_DoubleWord(Address, Data);
}
else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
{
/* Fast program a 32 row double-word (64-bit) at a specified address */
FLASH_Program_Fast(Address, (uint32_t)Data);
}
else
{
/* Nothing to do */
}
return status;
}
/**
* @brief Handle FLASH interrupt request.
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
uint32_t tmp_page;
uint32_t error;
FLASH_ProcedureTypeDef procedure;
/* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
defined (STM32L496xx) || defined (STM32L4A6xx) || \
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
#endif
/* Disable the FSTPG Bit only if it is the last row programmed */
if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
{
CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
}
/* Check FLASH operation error flags */
error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
if (error !=0U)
{
/*Save the error code*/
pFlash.ErrorCode |= error;
/* Clear error programming flags */
__HAL_FLASH_CLEAR_FLAG(error);
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
/* FLASH error interrupt user callback */
procedure = pFlash.ProcedureOnGoing;
if(procedure == FLASH_PROC_PAGE_ERASE)
{
HAL_FLASH_OperationErrorCallback(pFlash.Page);
}
else if(procedure == FLASH_PROC_MASS_ERASE)
{
HAL_FLASH_OperationErrorCallback(pFlash.Bank);
}
else if((procedure == FLASH_PROC_PROGRAM) ||
(procedure == FLASH_PROC_PROGRAM_LAST))
{
HAL_FLASH_OperationErrorCallback(pFlash.Address);
}
else
{
HAL_FLASH_OperationErrorCallback(0U);
}
/*Stop the procedure ongoing*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != 0U)
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
{
/* Nb of pages to erased can be decreased */
pFlash.NbPagesToErase--;
/* Check if there are still pages to erase*/
if(pFlash.NbPagesToErase != 0U)
{
/* Indicate user which page has been erased*/
HAL_FLASH_EndOfOperationCallback(pFlash.Page);
/* Increment page number */
pFlash.Page++;
tmp_page = pFlash.Page;
FLASH_PageErase(tmp_page, pFlash.Bank);
}
else
{
/* No more pages to Erase */
/* Reset Address and stop Erase pages procedure */
pFlash.Page = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Page);
}
}
else
{
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches() ;
procedure = pFlash.ProcedureOnGoing;
if(procedure == FLASH_PROC_MASS_ERASE)
{
/* MassErase ended. Return the selected bank */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
}
else if((procedure == FLASH_PROC_PROGRAM) ||
(procedure == FLASH_PROC_PROGRAM_LAST))
{
/* Program ended. Return the selected address */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
}
else
{
/* Nothing to do */
}
/*Clear the procedure ongoing*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
/* Disable End of Operation and Error interrupts */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
}
/**
* @brief FLASH end of operation interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Page Erase: Page which has been erased
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
* @brief FLASH operation error interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Page Erase: Page number which returned an error
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief Management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
* @{
*/
/**
* @brief Unlock the FLASH control register access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
HAL_StatusTypeDef status = HAL_OK;
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
/* Verify Flash is unlocked */
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Lock the FLASH control register access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
return HAL_OK;
}
/**
* @brief Unlock the FLASH Option Bytes Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
{
/* Authorizes the Option Byte register programming */
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Lock the FLASH Option Bytes Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
return HAL_OK;
}
/**
* @brief Launch the option byte loading.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
/* Set the bit to force the option byte reloading */
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
/* Wait for last operation to be completed */
return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode: The returned value can be:
* @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag
* @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
* @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag
* @arg HAL_FLASH_ERROR_NONE: No error set
* @arg HAL_FLASH_ERROR_OP: FLASH Operation error
* @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
* @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
* @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
* @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
* @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
* @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
* @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices)
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
uint32_t error;
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
{
if(Timeout != HAL_MAX_DELAY)
{
if((HAL_GetTick() - tickstart) >= Timeout)
{
return HAL_TIMEOUT;
}
}
}
error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
if(error != 0u)
{
/*Save the error code*/
pFlash.ErrorCode |= error;
/* Clear error programming flags */
__HAL_FLASH_CLEAR_FLAG(error);
return HAL_ERROR;
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
/* If there is an error flag set */
return HAL_OK;
}
/**
* @brief Program double-word (64-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Set PG bit */
SET_BIT(FLASH->CR, FLASH_CR_PG);
/* Program first word */
*(__IO uint32_t*)Address = (uint32_t)Data;
/* Barrier to ensure programming is performed in 2 steps, in right order
(independently of compiler optimization behavior) */
__ISB();
/* Program second word */
*(__IO uint32_t*)(Address+4U) = (uint32_t)(Data >> 32);
}
/**
* @brief Fast program a row double-word (64-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address where the data are stored.
* @retval None
*/
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
{
uint32_t primask_bit;
uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW);
__IO uint32_t *dest_addr = (__IO uint32_t*)Address;
__IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Set FSTPG bit */
SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
/* Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the double word of the row */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
row_index--;
} while (row_index != 0U);
/* Re-enable the interrupts */
__set_PRIMASK(primask_bit);
}
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

1316
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c Normal file
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251
Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c Normal file
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@ -0,0 +1,251 @@
/**
******************************************************************************
* @file stm32l4xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
* + FLASH HalfPage Programming
* + FLASH Power Down in Run mode
*
* @verbatim
==============================================================================
##### Flash RAM functions #####
==============================================================================
*** ARM Compiler ***
--------------------
[..] RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate
source module. Using the 'Options for File' dialog you can simply change
the 'Code / Const' area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the
Options for Target' dialog.
*** ICCARM Compiler ***
-----------------------
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
*** GNU Compiler ***
--------------------
[..] RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions -------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions
* @{
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### ramfunc functions #####
===============================================================================
[..]
This subsection provides a set of functions that should be executed from RAM.
@endverbatim
* @{
*/
/**
* @brief Enable the Power down in Run Mode
* @note This function should be called and executed from SRAM memory
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
{
/* Enable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_ENABLE();
return HAL_OK;
}
/**
* @brief Disable the Power down in Run Mode
* @note This function should be called and executed from SRAM memory
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
{
/* Disable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_DISABLE();
return HAL_OK;
}
#if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
/**
* @brief Program the FLASH DBANK User Option Byte.
*
* @note To configure the user option bytes, the option lock bit OPTLOCK must
* be cleared with the call of the HAL_FLASH_OB_Unlock() function.
* @note To modify the DBANK option byte, no PCROP region should be defined.
* To deactivate PCROP, user should perform RDP changing
*
* @param DBankConfig The FLASH DBANK User Option Byte value.
* This parameter can be one of the following values:
* @arg OB_DBANK_128_BITS: Single-bank with 128-bits data
* @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data
*
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)
{
uint32_t count, reg;
HAL_StatusTypeDef status = HAL_ERROR;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check if the PCROP is disabled */
reg = FLASH->PCROP1SR;
if (reg > FLASH->PCROP1ER)
{
reg = FLASH->PCROP2SR;
if (reg > FLASH->PCROP2ER)
{
/* Disable Flash prefetch */
__HAL_FLASH_PREFETCH_BUFFER_DISABLE();
if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
{
/* Disable Flash instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
/* Flush Flash instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
}
if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
{
/* Disable Flash data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
/* Flush Flash data cache */
__HAL_FLASH_DATA_CACHE_RESET();
}
/* Disable WRP zone 1 of 1st bank if needed */
reg = FLASH->WRP1AR;
if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <=
((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos))
{
MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT);
}
/* Disable WRP zone 2 of 1st bank if needed */
reg = FLASH->WRP1BR;
if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <=
((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos))
{
MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT);
}
/* Disable WRP zone 1 of 2nd bank if needed */
reg = FLASH->WRP2AR;
if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <=
((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos))
{
MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT);
}
/* Disable WRP zone 2 of 2nd bank if needed */
reg = FLASH->WRP2BR;
if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <=
((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos))
{
MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT);
}
/* Modify the DBANK user option byte */
MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig);
/* Set OPTSTRT Bit */
SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
/* Wait for last operation to be completed */
/* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */
count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U);
do
{
if (count == 0U)
{
break;
}
count--;
} while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET);
/* If the option byte program operation is completed, disable the OPTSTRT Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
/* Set the bit to force the option byte reloading */
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
}
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32l4xx_hal_gpio.c
* @author MCD Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
(++) Input mode
(++) Analog mode
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
(+) The external interrupt/event controller consists of up to 39 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
* range of the shift operator in following API :
* HAL_GPIO_Init
* HAL_GPIO_DeInit
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @addtogroup GPIO_Private_Defines GPIO Private Defines
* @{
*/
#define GPIO_NUMBER (16u)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00u;
uint32_t iocurrent;
uint32_t temp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
if (iocurrent != 0x00u)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
temp |= (GPIO_Init->Speed << (position * 2u));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
GPIOx->OTYPER = temp;
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/* In case of Analog mode, check if ADC control mode is selected */
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
{
/* Configure the IO Output Type */
temp = GPIOx->ASCR;
temp &= ~(GPIO_ASCR_ASC0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
GPIOx->ASCR = temp;
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
/* Activate the Pull-up or Pull down resistor for the current IO */
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
temp &= ~(0xFu << ((position & 0x07u) * 4u));
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
GPIOx->AFR[position >> 3u] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2u];
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
SYSCFG->EXTICR[position >> 2u] = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
{
temp |= iocurrent;
}
EXTI->RTSR1 = temp;
temp = EXTI->FTSR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
{
temp |= iocurrent;
}
EXTI->FTSR1 = temp;
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
{
temp |= iocurrent;
}
EXTI->EMR1 = temp;
temp = EXTI->IMR1;
temp &= ~(iocurrent);
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
{
temp |= iocurrent;
}
EXTI->IMR1 = temp;
}
}
position++;
}
}
/**
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00u;
uint32_t iocurrent;
uint32_t tmp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0x00u)
{
/* Get current io position */
iocurrent = (GPIO_Pin) & (1uL << position);
if (iocurrent != 0x00u)
{
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2u];
tmp &= (0x0FuL << (4u * (position & 0x03u)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
{
/* Clear EXTI line configuration */
EXTI->IMR1 &= ~(iocurrent);
EXTI->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->FTSR1 &= ~(iocurrent);
EXTI->RTSR1 &= ~(iocurrent);
tmp = 0x0FuL << (4u * (position & 0x03u));
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO in Analog Mode */
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
/* Deactivate the Control bit of Analog mode for the current IO */
GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
}
position++;
}
}
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Read the specified input port pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Set or clear the selected data port bit.
*
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
*
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
/**
* @brief Toggle the specified GPIO pin.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the pin to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
* @brief Lock GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32L4 family
* @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
/* Read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
}
/**
* @brief EXTI line detection callback.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file stm32l4xx_hal_i2c_ex.c
* @author MCD Application Team
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Filter Mode Functions
* + WakeUp Mode Functions
* + FastModePlus Functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32L4xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @brief Filter Mode Functions
*
@verbatim
===============================================================================
##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @brief WakeUp Mode Functions
*
@verbatim
===============================================================================
##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Wake Up Feature
@endverbatim
* @{
*/
/**
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @brief Fast Mode Plus Functions
*
@verbatim
===============================================================================
##### Fast Mode Plus Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Enable fast mode plus driving capability for selected pin */
SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
}
/**
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c Normal file
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@ -0,0 +1,658 @@
/**
******************************************************************************
* @file stm32l4xx_hal_pwr.c
* @author MCD Application Team
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Initialization/de-initialization functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/** @addtogroup STM32L4xx_HAL_Driver
* @{
*/
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PWR_Private_Defines PWR Private Defines
* @{
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
@endverbatim
* @{
*/
/**
* @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
* @retval None
*/
void HAL_PWR_DeInit(void)
{
__HAL_RCC_PWR_FORCE_RESET();
__HAL_RCC_PWR_RELEASE_RESET();
}
/**
* @brief Enable access to the backup domain
* (RTC registers, RTC backup data registers).
* @note After reset, the backup domain is protected against
* possible unwanted write accesses.
* @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
* In order to set or modify the RTC clock, the backup domain access must be
* disabled.
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
* back-up domain.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @brief Disable access to the backup domain
* (RTC registers, RTC backup data registers).
* @retval None
*/
void HAL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @brief Low Power modes configuration functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
*** PVD configuration ***
=========================
[..]
(+) The PVD is used to monitor the VDD power supply by comparing it to a
threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
(+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled. This is done through
__HAL_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in Standby mode.
*** WakeUp pin configuration ***
================================
[..]
(+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
The polarity of these pins can be set to configure event detection on high
level (rising edge) or low level (falling edge).
*** Low Power modes configuration ***
=====================================
[..]
The devices feature 8 low-power modes:
(+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
(+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
(+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
(+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
(+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
(+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
(+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
(+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
*** Low-power run mode ***
==========================
[..]
(+) Entry: (from main run mode)
(++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
(+) Exit:
(++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
then can the system clock frequency be increased above 2 MHz.
*** Sleep mode / Low-power sleep mode ***
=========================================
[..]
(+) Entry:
The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
(+) WFI Exit:
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) or any wake-up event.
(+) WFE Exit:
(++) Any wake-up event such as an EXTI line configured in event mode.
[..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
the MCU is in Low-power Run mode.
*** Stop 0, Stop 1 and Stop 2 modes ***
===============================
[..]
(+) Entry:
The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
(++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
(++) PWR_MAINREGULATOR_ON
(++) PWR_LOWPOWERREGULATOR_ON
(+) Exit (interrupt or event-triggered, specified when entering STOP mode):
(++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
(++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
(+) WFI Exit:
(++) Any EXTI Line (Internal or External) configured in Interrupt mode.
(++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
when programmed in wakeup mode.
(+) WFE Exit:
(++) Any EXTI Line (Internal or External) configured in Event mode.
[..]
When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
depending on the LPR bit setting.
When exiting Stop 2 mode, the MCU is in Run mode.
*** Standby mode ***
====================
[..]
The Standby mode offers two options:
(+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
and Standby circuitry.
(+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
SRAM and register contents are lost except for the RTC registers, RTC backup registers
and Standby circuitry.
(++) Entry:
(+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
to set RRS bit.
(++) Exit:
(+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
external reset in NRST pin, IWDG reset.
[..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
*** Shutdown mode ***
======================
[..]
In Shutdown mode,
voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
SRAM and registers contents are lost except for backup domain registers.
(+) Entry:
The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
external reset in NRST pin.
[..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
*** Auto-wakeup (AWU) from low-power mode ***
=============================================
[..]
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
Wakeup event, a tamper event or a time-stamp event, without depending on
an external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
is necessary to configure the RTC to detect the tamper or time stamp event using the
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
*/
/**
* @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
* @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD
* configuration information.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage thresholds corresponding to each
* detection level.
* @retval None
*/
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
/* Set PLS bits according to PVDLevel value */
MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
/* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT();
}
/* Configure event mode */
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
/* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
return HAL_OK;
}
/**
* @brief Enable the Power Voltage Detector (PVD).
* @retval None
*/
void HAL_PWR_EnablePVD(void)
{
SET_BIT(PWR->CR2, PWR_CR2_PVDE);
}
/**
* @brief Disable the Power Voltage Detector (PVD).
* @retval None
*/
void HAL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
}
/**
* @brief Enable the WakeUp PINx functionality.
* @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
* This parameter can be one of the following legacy values which set the default polarity
* i.e. detection on high level (rising edge):
* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
*
* or one of the following value where the user can explicitly specify the enabled pin and
* the chosen polarity:
* @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
* @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
* @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
* @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
* @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
{
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
/* Specifies the Wake-Up pin polarity for the event detection
(rising or falling edge) */
MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
/* Enable wake-up pin */
SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
}
/**
* @brief Disable the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
}
/**
* @brief Enter Sleep or Low-power Sleep mode.
* @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
* @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
* This parameter can be one of the following values:
* @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
* @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
* @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
* in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
* to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
* Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
* Additionally, the clock frequency must be reduced below 2 MHz.
* Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
* be done before calling HAL_PWR_EnterSLEEPMode() API.
* @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
* Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
* @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
* @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
* @note When WFI entry is used, tick interrupt have to be disabled if not desired as
* the interrupt wake up source.
* @retval None
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Set Regulator parameter */
if (Regulator == PWR_MAINREGULATOR_ON)
{
/* If in low-power run mode at this point, exit it */
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
{
if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
{
return ;
}
}
/* Regulator now in main mode. */
}
else
{
/* If in run mode, first move to low-power run mode.
The system clock frequency must be below 2 MHz at this point. */
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
{
HAL_PWREx_EnableLowPowerRunMode();
}
}
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
}
/**
* @brief Enter Stop mode
* @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
* on devices where only "Stop mode" is mentioned with main or low power regulator ON.
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
* the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
* (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
* after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
* only to the peripheral requesting it.
* SRAM1, SRAM2 and register contents are preserved.
* The BOR is available.
* The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
* @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
* is set; the MSI oscillator is selected if STOPWUCK is cleared.
* @note When the voltage regulator operates in low power mode (Stop 1), an additional
* startup delay is incurred when waking up.
* By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
* is higher although the startup time is reduced.
* @param Regulator: Specifies the regulator state in Stop mode.
* This parameter can be one of the following values:
* @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
* @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
* @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
* @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
* @retval None
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
if(Regulator == PWR_LOWPOWERREGULATOR_ON)
{
HAL_PWREx_EnterSTOP1Mode(STOPEntry);
}
else
{
HAL_PWREx_EnterSTOP0Mode(STOPEntry);
}
}
/**
* @brief Enter Standby mode.
* @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
* off. The voltage regulator is disabled, except when SRAM2 content is preserved
* in which case the regulator is in low-power mode.
* SRAM1 and register contents are lost except for registers in the Backup domain and
* Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
* To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
* to set RRS bit.
* The BOR is available.
* @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
* HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
* Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
* same.
* These states are effective in Standby mode only if APC bit is set through
* HAL_PWREx_EnablePullUpPullDownConfig() API.
* @retval None
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
/* Set Stand-by mode */
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}
/**
* @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run only on
* interruptions handling.
* @retval None
*/
void HAL_PWR_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
* @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* @retval None
*/
void HAL_PWR_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enable CORTEX M4 SEVONPEND bit.
* @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_EnableSEVOnPend(void)
{
/* Set SEVONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Disable CORTEX M4 SEVONPEND bit.
* @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_DisableSEVOnPend(void)
{
/* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief PWR PVD interrupt callback
* @retval None
*/
__weak void HAL_PWR_PVDCallback(void)
{
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_PWR_PVDCallback can be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/

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